64Mb: x32 SDRAM
Clock Suspend
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls when an in-
ternal clock edge is suspended will be ignored; any data present on the DQ balls re-
mains driven; and burst counters are not incremented, as long as the clock is suspen-
ded.
Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-
tion will resume on the subsequent positive clock edge.
Figure 49: Clock Suspend During WRITE Burst
T0
CLK
T1
T2
T3
T4
T5
CKE
Internal
clock
Command
NOP
WRITE
NOP
NOP
Address
Bank,
Col n
D
IN
D
IN
D
IN
D
IN
Don’t Care
Note:
1. For this example, BL = 4 or greater, and DQM is LOW.
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
78
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