64Mb: x32 SDRAM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 7: Absolute Maximum Ratings
Voltage/Temperature
Voltage on V
DD
, V
DDQ
supply relative to V
SS
Voltage on inputs, NC, or I/O pins relative to V
SS
Storage temperature (plastic)
Power dissipation
Symbol
V
DD
, V
DDQ
V
IN
T
STG
–
Min
–1
–1
–55
–
Max
4.6
4.6
150
1
Unit
V
V
°C
W
Table 8: DC Electrical Characteristics and Operating Conditions
Notes 1–3 apply to all parameters and conditions; V
DD
, V
DDQ
= 3.3V ±0.3V
Parameter/Condition
Symbol
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output high voltage: I
OUT
= –4mA
Output low voltage: I
OUT
= 4mA
Input leakage current: Any input 0V
≤
V
IN
≤
V
DD
(All other pins
not under test = 0V)
Output leakage current: DQs are disabled; 0V
≤
V
OUT
≤
V
DDQ
Operating temperature:
Commercial
Industrial
Automotive
Notes:
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
L
I
OZ
T
A
T
A
T
A
Min
3
2
–0.3
2.4
–
–5
–5
0
–40
–40
Max
3.6
V
DD
+ 0.3
0.8
–
0.4
5
5
70
85
105
Unit
V
V
V
V
V
μA
μA
°C
°C
°C
Notes
1. All voltages referenced to V
SS
.
2. An initial pulse of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured (V
DD
and V
DDQ
must be powered
up simultaneously. V
SS
and V
SSQ
must be at same potential). The two AUTO REFRESH
command wake-ups should be repeated any time the
t
REF refresh requirement is excee-
ded.
3. V
DD,min
= 3.135V for -6, -55, and -5 speed grades.
4. V
IH
overshoot: V
IH,max
= V
DDQ
+ 1.2V for a pulse width
≤
3ns, and the pulse width cannot
be greater than one-third of the cycle rate. V
IL
undershoot: V
IL,min
= –1.2V for a pulse
width
≤3ns,
and the pulse width cannot be greater than one-third of the cycle rate.
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
17
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©
1999 Micron Technology, Inc. All rights reserved.