64Mb: x32 SDRAM
Pin and Ball Assignments and Descriptions
Table 4: Pin and Ball Descriptions
Symbol
Type Description
CLK
Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE
Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-
gress). CKE is synchronous except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-
cluding CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
CS#
Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-
coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already
in progress will continue, and DQM operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
CAS#, RAS#,
WE#
Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-
tered.
DQM[3:0]
Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0
corresponds to DQ[7:0]; DQM1 corresponds to DQ[15:8]; DQM2 corresponds to DQ[23:16]; and
DQM3 corresponds to DQ[31:24]. DQM[3:0] are considered same state when referenced as
DQM.
BA[1:0]
A[10:0]
Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied.
Input Address inputs: A[10:0] are sampled during the ACTIVE command (row address A[10:0]) and
READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select
one location out of the memory array in the respective bank. A10 is sampled during a PRE-
CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec-
ted by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
DQ[31:0]
VDDQ
VSSQ
VDD
I/O
Data input/output: Data bus.
Supply DQ power supply: DQ power to the die for improved noise immunity.
Supply DQ ground: DQ ground to the die for improved noise immunity.
Supply Power supply: 3.3V ±0.3V.
VSS
Supply Ground.
NC
–
–
No connect: These pins/balls should be left unconnected.
NU
Not used.
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
11
MICRON [ MICRON TECHNOLOGY ]
