Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
Description
Min
Max
Power-down entry transition period
(power-down entry)
Greater of: tANPD or tRFC - refresh to CKE LOW
tANPD + tXPDLL
Power-down exit transition period
(power-down exit)
ODT to RTT turn-on delay
(ODTLon = WL - 2)
Lesser of: tAONPD (MIN) (2ns) or
ODTLon × tCK + tAON (MIN)
Greater of: tAONPD (MAX) (8.5ns) or
ODTLon × tCK + tAON (MAX)
ODT to RTT turn-off delay
(ODTLoff = WL - 2)
Lesser of: tAOFPD (MIN) (2ns) or
ODTLoff × tCK + tAOF (MIN)
Greater of: tAOFPD (MAX) (8.5ns) or
ODTLoff × tCK + tAOF (MAX)
tANPD
WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)
Figure 119: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Ta0
Ta1
Ta2
Ta3
CK#
CK
CKE
Command
NOP
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tRFC (MIN)
tANPD
PDE transition period
ODT A
synchronous
tAOF (MIN)
tAOF (MAX)
DRAM R
A
TT
R
TT,nom
synchronous
ODTLoff + tAOFPD (MIN)
tAOFPD (MAX)
ODTLoff
ODT B
asynchronous
or synchronous
tAOFPD (MIN)
DRAM R
asynchronous
B
TT
R
TT,nom
ODTLoff + tAOFPD (MAX)
or synchronous
ODT C
asynchronous
tAOFPD (MIN)
tAOFPD (MAX)
DRAM R
C
R
TT
TT,nom
asynchronous
Indicates break
in time scale
Transitioning
Don’t Care
1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.
Note:
MICRON [ MICRON TECHNOLOGY ]
