4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE
WE#-CONTROLLED WRITE/ERASE
VIH
VIL
A0–A17/(A18)
Note 1
AIN
t
t
AH
t
t
AH
AS
AS
VIH
VIL
CE#
OE#
t
t
CH
CS
VIH
VIL
t
WC
t
WP
t
t
WED1/2/3/4
WPH
VIH
VIL
t
WB
WE#
t
t
DH
DH
t
t
DS
DS
VIH
VIL
Status
(SR7=0)
CMD
in
CMD/
Data-in
Status
(SR7=1)
CMD
in
DQ0–DQ7/
DQ0–DQ15 2
t
t
t
RS
RHS
RHH
[Unlock boot block]
VHH
VIH
RP# 3
VIL
[Unlock boot block]
VIH
WP# 3
VIL
t
VPS1
t
t
VPS2
VPH
[5V VPP
]
VPPH2
VPPH1
VPPLK
[3.3V VPP
]
VPP
VIL
WRITE or ERASE (block)
address asserted, and
WRITE data or ERASE
CONFIRM issued
WRITE or ERASE
executed, status register
checked for completion
Command for next
operation issued
WRITE SETUP or
ERASE SETUP input
DON’T CARE
TIMING PARAMETERS
Commercial Temperature (0ºC £ TA £ +70ºC)
Extended Temperature (-40ºC £ TA £ +85ºC)
-8/-8 ET
-8/-8 ET
SYMBOL
MIN
80
20
50
50
0
MAX UNITS
SYMBOL
MIN
MAX UNITS
t
t
WC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VPS2
100
1,000
100
2
ns
ns
ns
µs
ms
ms
ms
ns
ns
ns
t
t
WPH
RS
t
t
WP
RHS
t
t
AS
WED1
t
t
AH
WED2
100
100
500
200
0
t
t
DS
50
0
WED3
t
t
DH
WED4
t
t
CS
0
WB
t
t
CH
0
VPH
t
t
VPS1
200
RHH
0
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F400B3
only).
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
4MbSmart3BootBlockFlashMemory
F45_3.p65 – Rev. 3, Pub. 12/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
25
MICRON [ MICRON TECHNOLOGY ]
