512Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Bus Operations
Bus Operations
Table 3: Bus Operations
Notes 1 and 2 apply to entire table
8-Bit Mode
16-Bit Mode
DQ15/A-1,
A[MAX:0],
DQ15/A-1
Operation CE# OE# WE# RST# VPP/WP#
DQ[14:8]
High-Z
DQ[7:0]
A[MAX:0]
DQ[14:0]
Data output
Data input4
READ
L
L
L
H
L
H
H
X
Address
Data output
Data input4
Address
WRITE
H
H3
Command
address
High-Z
Command
address
STANDBY
H
L
X
H
X
H
H
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
X
X
High-Z
High-Z
OUTPUT
DISABLE
RESET
X
X
X
L
X
X
High-Z
High-Z
X
High-Z
1. Typical glitches of less than 3ns on CE#, OE#, and WE# are ignored by the device and do
not affect bus operations.
Notes:
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# is LOW, then the highest or the lowest block remains protected, depending on
line item.
4. Data input is required when issuing a command sequence or when performing data
polling or block protection.
Read
Bus READ operations read from the memory cells, registers, extended memory block, or
CFI space. To accelerate the READ operation, the memory array can be read in page
mode where data is internally read and stored in a page buffer.
Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus
mode and A[3:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI
area support page read mode.
A valid bus READ operation involves setting the desired address on the address inputs,
taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value.
If CE# goes HIGH and returns LOW for a subsequent access, a random read access is
performed and tACC or tCE is required. (See AC Characteristics for details about when
the output becomes valid).
Write
Bus WRITE operations write to the command interface. A valid bus WRITE operation
begins by setting the desired address on the address inputs. The address inputs are
latched by the command interface on the falling edge of CE# or WE#, whichever occurs
last. The data I/Os are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE oper-
ation (See AC Characteristics for timing requirement details).
PDF: 09005aef855e354a
mt28ew_generation-b_512mb.pdf - Rev. I 05/18 EN
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