256Mb, 3V Multiple I/O Serial Flash Memory
Features
Figure 51: Reset Enable and Reset Memory Timing ......................................................................................... 92
Figure 52: Serial Input Timing STR ................................................................................................................. 92
Figure 53: Serial Input Timing DTR ................................................................................................................ 93
Figure 54: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 93
Figure 55: Hold Timing .................................................................................................................................. 93
Figure 56: Output Timing for STR ................................................................................................................... 94
Figure 57: Output Timing for DTR .................................................................................................................. 94
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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