256Mb, 3V Multiple I/O Serial Flash Memory
Power-Up and Power-Down
Figure 48: Power-Up Timing
VCC
VCC,max
Chip selection not allowed
VCC,min
tVSL
Chip
reset
Device fully accessible
Polling allowed
VWI
Extended-SPI protocol
Status register bit 0 = 1
Flag status register bit 7 = 0
Time
1. tVSL polling has to be in extended-SPI protocol and STR mode.
2. During tVSL period, HOLD# is enabled, RESET# disabled, and output strength is in de-
fault setting.
Notes:
3. In a system that uses a fast VCC ramp rate, current design requires a minimum 100µs af-
ter VCC reaches tVWI, and before the polling is allowed, even though VCC,min is achieved.
4. In extended-SPI protocol, 1Gb and 2Gb device must wait 100µs after VCC reaches VCC,min
before polling the status register or flag status register.
Table 41: Power-Up Timing and VWI Threshold
Note 1 applies to entire table
Symbol
tVSL
Parameter
Min
–
Max
300
2.5
Unit
µs
Notes
2, 3
2
VCC,min to device fully accessible
Write inhibit voltage
VWI
1.5
V
1. When VCC reaches VCC,min, to determine whether power-up initialization is complete,
the host can poll status register bit 0 or flag status register bit 7 only in extended-SPI
protocol because the device will accept commands only on DQ0 and output data only
on DQ1. When the device is ready, the host has full access using the protocol configured
in the nonvolatile configuration register. If the host cannot poll the status register in x1
SPI mode, it is recommended to wait tVSL before accessing the device.
Notes:
2. Parameters listed are characterized only.
3. On the first power-up after an event causing a subsector erase operation interrupt (for
example, due to power-loss), the maximum time for tVSL will be up to 4.5ms in case of
4KB subsector erase interrupt and up to 36ms in case of 32KB subsector erase interrupt;
this accounts for erase recovery embedded operation.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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