256Mb, 3V Multiple I/O Serial Flash Memory
Power-Up and Power-Down
Power-Up and Power-Down
Power-Up and Power-Down Requirements
At power-up and power-down, the device must not be selected; that is, S# must follow
the voltage applied on VCC until VCC reaches the correct values: VCC,min at power-up and
VSS at power-down.
To provide device protection and prevent data corruption and inadvertent WRITE oper-
ations during power-up, a power-on reset circuit is included. The logic inside the device
is held to RESET while VCC is less than the power-on reset threshold voltage shown here;
all operations are disabled, and the device does not respond to any instruction. During
a standard power-up phase, the device ignores all commands except READ STATUS
REGISTER and READ FLAG STATUS REGISTER. These operations can be used to check
the memory internal state. After power-up, the device is in standby power mode; the
write enable latch bit is reset; the write in progress bit is reset; and the dynamic protec-
tion register is configured as: (write lock bit, lock down bit) = (0,0).
Normal precautions must be taken for supply line decoupling to stabilize the VCC sup-
ply. Each device in a system should have the VCC line decoupled by a suitable capacitor
(typically 100nF) close to the package pins. At power-down, when VCC drops from the
operating voltage to below the power-on-reset threshold voltage shown here, all opera-
tions are disabled and the device does not respond to any command.
When the operation is in progress, the program or erase controller bit of the status reg-
ister is set to 0. To obtain the operation status, the flag status register must be polled.
When the operation completes, the program or erase controller bit is cleared to 1. The
cycle is complete after the flag status register outputs the program or erase controller bit
to 1.
Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,
data corruption may result.
Note: In extended-SPI protocol, 1Gb and 2Gb device must wait 100µs after VCC reaches
VCC,min before polling the status register or flag status register.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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