256Mb, 3V Multiple I/O Serial Flash Memory
CYCLIC REDUNDANCY CHECK Operations
CYCLIC REDUNDANCY CHECK Operations
A CYCLIC REDUNDANCY CHECK (CRC) operation is a hash function designed to de-
tect accidental changes to raw data and is used commonly in digital networks and stor-
age devices such as hard disk drives. A CRC-enabled device calculates a short, fixed-
length binary sequence, known as the CRC code or just CRC, for each block of data. CRC
can be a higher performance alternative to reading data directly in order to verify re-
cently programmed data. Or, it can be used to check periodically the data integrity of a
large block of data against a stored CRC reference over the life of the product. CRC helps
improve test efficiency for programmer or burn-in stress tests. No system hardware
changes are required to enable CRC.
The CRC-64 operation follows the ECMA standard. The generating polynomial is:
G(x) = x64 + x62 + x57 + x55 + x54 + x53 + x52 + x47 + x46 + x45 + x40 + x39 + x38 + x37 + x35 + x33
+ x32 + x31 + x29 + x27 + x24 + x23 + x22 + x21 + x19 + x17 + x13 + x12 + x10 + x9 + x7 + x4 + x + 1
Note: The data stream sequence is from LSB to MSB and the default initial CRC value is
all zero.
The device CRC operation generates the CRC result of the entire device or of an address
range specified by the operation. Then the CRC result is compared with the expected
CRC data provided in the sequence. Finally the device indicates a pass or fail through
the bit #4 of FLAG STATUS REGISTER. If the CRC fails, it is possible to take corrective
action such as verifying with a normal read mode or by rewriting the array data.
CRC operation supports CRC data read back when CRC check fails; the CRC data gener-
ated from the target address range or entire device will be stored in a dedicated register:
general purpose read register (GPRR) only when CRC check fails, and it can be read out
through the GPRR read sequence with command 96h, least significant byte first. GPRR
is reset to default all 0 at the beginning of the CRC operation, and so customer will read
all 0 if CRC operation pass.
Note that the GPRR is a volatile register. It is cleared to all 0s on power-up and hard-
ware/software reset. Read GPRR starts from the first location, when clocked continu-
ously, will output 00h after location 64.
The CYCLIC REDUNDANCY CHECK operation command sequences are shown in the
tables below, for an entire die or for a selected range.
Table 36: CRC Command Sequence on Entire Device
Command Sequence
Byte#
Data
9Bh
Description
1
2
Command code for interface activation
Sub-command code for CRC operation
CRC operation option selection (CRC operation on entire device)
1st byte of expected CRC value
27h
3
FFh
4
CRC[7:0]
CRC[55:8]
CRC[63:56]
5–10
11
2nd to 7th byte of expected CRC value
8th byte of expected CRC value
Drive S# HIGH
Operation sequence confirmed; CRC operation starts
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
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