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MT250QL01GABA3EW70AITES 参数 Datasheet PDF下载

MT250QL01GABA3EW70AITES图片预览
型号: MT250QL01GABA3EW70AITES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb, 3V Multiple I/O Serial Flash Memory  
Volatile Configuration Register  
Volatile Configuration Register  
This register is read from and written to by the READ VOLATILE CONFIGURATION  
REGISTER and the WRITE VOLATILE CONFIGURATION REGISTER commands, respec-  
tively. A register download is executed after these commands, overwriting the internal  
configuration register settings that determine device memory behavior.  
Table 8: Volatile Configuration Register  
Bit  
Name  
Settings  
Description  
Notes  
7:4  
Number of  
dummy clock 0001 = 1  
0000 = Identical to 1111  
Sets the number of dummy clock cycles subsequent to all  
FAST READ commands.  
1
cycles  
0010 = 2  
(See the Command Set Table for default setting values.)  
1101 = 13  
1110 = 14  
1111 = Default  
3
XIP  
0 = Enable  
1 = Disable (Default)  
Enables or disables XIP.  
0b = Fixed value.  
2
Reserved  
Wrap  
0
1:0  
00 = 16-byte boundary  
aligned  
16-byte wrap: Output data wraps within an aligned 16-byte  
boundary starting from the 3-byte address issued after the  
command code.  
2
01 = 32-byte boundary  
aligned  
32-byte wrap: Output data wraps within an aligned 32-byte  
boundary starting from the 3-byte address issued after the  
command code.  
10 = 64-byte boundary  
aligned  
64-byte wrap: Output data wraps within an aligned 64-byte  
boundary starting from the 3-byte address issued after the  
command code.  
11 = Continuous (Default) Continuously sequences addresses through the entire array.  
1. The number of cycles must be set according to and sufficient for the clock frequency,  
which varies by the type of FAST READ command, as shown in the Supported Clock Fre-  
quencies table. An insufficient number of dummy clock cycles for the operating frequen-  
cy causes the memory to read incorrect data.  
Notes:  
2. See the Sequence of Bytes During Wrap table.  
Table 9: Sequence of Bytes During Wrap  
Starting Address  
16-Byte Wrap  
32-Byte Wrap  
64-Byte Wrap  
0-1-2- . . . -63-0-1- . .  
1-2- . . . -63-0-1-2- . .  
....  
0
0-1-2- . . . -15-0-1- . .  
0-1-2- . . . -31-0-1- . .  
1
1-2- . . . -15-0-1-2- . .  
1-2- . . . -31-0-1-2- . .  
....  
15  
....  
31  
....  
63  
....  
....  
15-0-1-2-3- . . . -15-0-1- . .  
15-16-17- . . . -31-0-1- . .  
15-16-17- . . . -63-0-1- . .  
....  
....  
....  
31-0-1-2-3- . . . -31-0-1- . .  
31-32-33- . . . -63-0-1- . .  
....  
....  
....  
63-0-1- . . . -63-0-1- . .  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 2014 Micron Technology, Inc. All rights reserved.  
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