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MT250QL01GABA3EW70AITES 参数 Datasheet PDF下载

MT250QL01GABA3EW70AITES图片预览
型号: MT250QL01GABA3EW70AITES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb, 3V Multiple I/O Serial Flash Memory  
Signal Descriptions  
Signal Descriptions  
The signal description table below is a comprehensive list of signals for the MT25Q fam-  
ily devices. All signals listed may not be supported on this device. See Signal Assign-  
ments for information specific to this device.  
Table 1: Signal Descriptions  
Symbol  
Type  
Description  
S#  
Input  
Chip select: When S# is driven HIGH, the device will enter standby mode, unless an internal  
PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress. All other input pins are ig-  
nored and the output pins are tri-stated. On parts with the pin configuration offering a dedica-  
ted RESET# pin, however, the RESET# input pin remains active even when S# is HIGH.  
Driving S# LOW enables the device, placing it in the active mode.  
After power-up, a falling edge on S# is required prior to the start of any command.  
C
Input  
Input  
Clock: Provides the timing of the serial interface. Command inputs are latched on the rising  
edge of the clock. In STR commands or protocol, address and data inputs are latched on the  
rising edge of the clock, while data is output on the falling edge of the clock. In DTR com-  
mands or protocol, address and data inputs are latched on both edges of the clock, and data is  
output on both edges of the clock.  
RESET#  
RESET#: When RESET# is driven LOW, the device is reset and the outputs are tri-stated. If RE-  
SET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, da-  
ta may be lost. The RESET# functionality can be disabled using bit 4 of the nonvolatile configu-  
ration register or bit 4 of the enhanced volatile configuration register.  
For pin configurations that share the DQ3 pin with RESET#, the RESET# functionality is disabled  
in QIO-SPI mode.  
HOLD#  
Input  
Input  
HOLD: Pauses serial communications with the device without deselecting or resetting the de-  
vice. Outputs are tri-stated and inputs are ignored. The HOLD# functionality can be disabled  
using bit 4 of the nonvolatile configuration register or bit 4 of the enhanced volatile configura-  
tion register.  
For pin configurations that share the DQ3 pin with HOLD#, the HOLD# functionality is disabled  
in QIO-SPI mode or when DTR operation is enabled.  
W#  
Write protect: Freezes the status register in conjunction with the enable/disable bit of the sta-  
tus register. When the enable/disable bit of the status register is set to 1 and the W# signal is  
driven LOW, the status register nonvolatile bits become read-only and the WRITE STATUS REG-  
ISTER operation will not execute. During the extended-SPI protocol with QOFR and QIOFR in-  
structions, and with QIO-SPI protocol, this pin function is an input/output as DQ2 functionality.  
This signal does not have internal pull-ups, it cannot be left floating and must be driven, even  
if none of W#/DQ2 function is used.  
DQ[3:0]  
I/O  
Serial I/O: The bidirectional DQ signals transfer address, data, and command information.  
When using legacy (x1) SPI commands in extended I/O protocol (XIO-SPI), DQ0 is an input and  
DQ1 is an output. DQ[3:2] are not used.  
When using dual commands in XIO-SPI or when using DIO-SPI, DQ[1:0] are I/O. DQ[3:2] are not  
used.  
When using quad commands in XIO-SPI or when using QIO-SPI, DQ[3:0] are I/O.  
Core and I/O power supply.  
VCC  
Supply  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
15  
© 2014 Micron Technology, Inc. All rights reserved.  
 
 
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