256Mb, 3V Multiple I/O Serial Flash Memory
READ REGISTER Operations
READ REGISTER Operations
To initiate a command, S# is driven LOW. For extended SPI protocol, input is on DQ0,
output on DQ1. For dual SPI protocol, input/output is on DQ[1:0] and for quad SPI pro-
tocol, input/output is on DQ[3:0]. The operation is terminated by driving S# HIGH at
any time during data output.
Table 25: READ REGISTER Operations
Operation Name
Description/Conditions
Note
READ STATUS REGISTER (05h)
READ FLAG STATUS REGISTER (70h)
Can be read continuously and at any time, including during a PRO-
GRAM, ERASE, or WRITE operation. If one of these operations is in
progress, checking the write in progress bit or P/E controller bit is
recommended before executing the command.
READ NONVOLATILE CONFIGURATION
REGISTER (B5h)
Can be read continuously. After all 16 bits of the register have been
read, a 0 is output. All reserved fields output a value of 1.
1
READ VOLATILE CONFIGURATION REGIS-
TER (85h)
When the register is read continuously, the same byte is output re-
peatedly.
READ ENHANCED VOLATILE CONFIGURA-
TION REGISTER (65h)
READ EXTENDED ADDRESS REGISTER (C8h)
1. The operation will have output data starting from the least significant byte.
Note:
Figure 32: READ REGISTER Timing
Extended
0
7
8
9
10
11
12
13
14
15
C
DQ0
DQ1
LSB
Command
High-Z
MSB
LSB
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Dual
0
3
4
5
6
7
C
LSB
LSB
DOUT
DOUT
DOUT
DOUT
DOUT
MSB
DQ[1:0]
Command
MSB
Quad
0
1
2
3
C
LSB
LSB
DOUT
DOUT
MSB
DOUT
DQ[3:0]
Command
Don’t Care
MSB
1. Supports all READ REGISTER commands except DYNAMIC PROTECTION BITS READ.
Notes:
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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