256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Co m m a n d s
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available com m ands. For a m ore detailed description
of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data sheet.
Ta b le 8:
Co m m a n d s Tru t h Ta b le
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
CS#
RAS#
CAS#
WE#
ADDR
NOTES
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
1
1
DESELECT (NOP)
NO OPERATION (NOP)
Bank/Row
Bank/Col
Bank/Col
X
2
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
H
H
H
L
3
L
3
H
H
L
L
4
L
Code
5
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
L
H
L
X
6, 7
8
L
L
Op-Code
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide row address.
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide column address; A10
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12
(256MB, 512MB) provide the op-code to be written to the selected mode register.
Ta b le 9:
DM Op e ra t io n Tru t h Ta b le
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
DM
DQS
L
Valid
X
WRITE Enable
WRITE Inhibit
H
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
11
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