256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Ta b le 19: Se ria l Pre se n ce -De t e ct EEPROM DC Op e ra t in g Co n d it io n s
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
VDDSPD
VIH
VIL
2.3
3.6
V
V
SUPPLY VOLTAGE
VDD × 0.7 VDD + 0.5
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
-1
–
VDD + 0.3
V
VOL
ILI
0.4
10
10
30
2
V
OUTPUT LOW VOLTAGE: IOUT = 3mA
–
µA
µA
µA
mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
ILO
–
ISB
–
ICC
–
Ta b le 20: Se ria l Pre se n ce -De t e ct EEPROM AC Op e ra t in g Co n d it io n s
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN MAX UNITS
NOTES
tAA
tBUF
tDH
0.2
1.3
0.9
µs
µs
1
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
200
ns
tF
300
ns
2
SDA and SCL fall time
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
0
µs
Data-in hold time
0.6
0.6
µs
Start condition hold time
Clock HIGH period
µs
50
ns
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
1.3
µs
0.3
µs
2
SDA and SCL rise time
fSCL
400
KHz
ns
SCL clock frequency
tSU:DAT
tSU:STA
tSU:STO
tWRC
100
0.6
0.6
Data-in setup time
µs
3
4
Start condition setup time
Stop condition setup time
WRITE cycle time
µs
10
ms
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
26
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