512MB, 1GB (x72, ECC, SR) PC3200
184-PIN DDR SDRAM RDIMM
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER com m and is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER com m and to select norm al operat-
ing mode.
All other combinations of values for A7–A12 are
reserved for future use and/ or test m odes. Test m odes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
DLL En a b le /Disa b le
The DLL m ust be enabled for norm al operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh m ode, the DLL
is enabled automatically.) Any time the DLL is enabled,
a DLL Reset and 200 clock cycles with CKE HIGH must
occur before a READ com m and can be issued.
Fig u re 7: Ext e n d e d Mo d e Re g ist e r
De fin it io n Dia g ra m
Ext e n d e d Mo d e Re g ist e r
A8
A9
A6 A5 A4
A1
A0
Address Bus
BA1
A10
A7
A3 A2
BA0 A12 A11
The extended m ode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/ disable and out-
put drive strength. These functions are controlled via
the bits shown in the Extended Mode Register Defini-
tion Diagram. The extended mode register is pro-
grammed via the LOAD MODE REGISTER command
to the mode register (with BA0 = 1 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/ BA1 both LOW) to reset the DLL.
The extended mode register m ust be loaded when
all device banks are idle and no bursts are in progress,
and the controller m ust wait the specified tim e before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Extended Mode
Register (Ex)
1
1
0
1
Operating Mode
DS DLL
DLL
E0
0
1
Enable
Disable
Drive Strength
E1
0
Normal
2
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2
E1, E0
Valid
–
Operating Mode
Reserved
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
Reserved
NOTE:
1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Register).
2. QFC# is not supported.
pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
11
MICRON [ MICRON TECHNOLOGY ]
