512MB, 1GB (x72, ECC, SR) PC3200
184-PIN DDR SDRAM RDIMM
Ta b le 6:
Bu rst De fin it io n Ta b le
Fig u re 6: CAS La t e n cy Dia g ra m
T0
T1
T2
T2n
T3
T3n
ORDER OF ACCESSES WITHIN
A BURST
CK#
CK
STARTING
COLUMN
ADDRESS
BURST
LENGTH
TYPE =
TYPE =
READ
NOP
NOP
NOP
COMMAND
SEQUENTIAL INTERLEAVED
CL = 3
A0
2
4
DQS
DQ
0
1
0-1
1-0
0-1
1-0
A1 A0
T0
T1
T2
T2n
T3
T3n
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CK#
CK
COMMAND
READ
NOP
NOP
NOP
CL = 2.5
A2 A1 A0
DQS
DQ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
8
T0
T1
T2
T2n
T3
T3n
CK#
CK
COMMAND
READ
NOP
NOP
NOP
CL = 2
DQS
DQ
NOTE:
1. For a burst length of two, A1–Ai select the two-data-
element block; A0 selects the first access within the
block.
Burst Length = 4 in the cases shown
Shown with nominal AC, DQSCK, and DQSQ
t
t
t
TRANSITIONING DATA DON’T CARE
2. For a burst length of four, A2–Ai select the four-data-
element block; A0–A1 select the first access within the
block.
3. For a burst length of eight, A3–Ai select the eight-data-
element block; A0–A2 select the first access within the
block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
Re a d La t e n cy
The READ latency is the delay, in clock cycles,
between the registration of a READ com m and and the
availability of the first bit of output data. The latency
can be set to 3, 2.5, or 2 clocks, as shown in Figure 6,
CAS Latency Diagram.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used, because un-
known operation or incompatibility with future ver-
sions may result.
5. i = 9, 11 (512MB)
i = 9, 11, 12 (1GB)
Ta b le 7:
CAS La t e n cy (CL) Ta b le
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED
CL = 2
CL = 2.5
CL = 3
Op e ra t in g Mo d e
-40B
75 ≤ f ≤ 133
75 ≤ f ≤ 133
133 ≤ f ≤ 200
The normal operating mode is selected by issuing a
MODE REGISTER SET com m and with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
10
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