512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
Mo d e Re g ist e r De fin it io n
Fig u re 6:
CAS La t e n cy Dia g ra m
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
AC
CAS latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS latency = 3
DON’T CARE
UNDEFINED
CAS La t e n cy
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 6. Table 7 on page 13, indicates the operating
frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Op e ra t in g Mo d e
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/ or test modes. The pro-
grammed burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
12
©2002 Micron Technology, Inc. All rights reserved.
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