512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
Mo d e Re g ist e r De fin it io n
Fig u re 5:
Mo d e Re g ist e r De fin it io n Dia g ra m
A12 A11
A8
A6 A5 A4
A1
Address Bus
A10
A7
A3 A2
A0
A9
12
11
9
8
6
5
4
1
10
7
3
2
0
Mode Register (Mx)
Reserved
WB Op Mode
CAS Latency
BT
Burst Length
Program
Burst Length
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6–M0
Defined
-
Operating Mode
0
-
0
-
Standard Operation
All Other States Reserved
Write Burst Mode
M9
0
1
Programmed Burst Length
Single Location Access
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
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