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MT18JDF1G72PDZ-1G1__ 参数 Datasheet PDF下载

MT18JDF1G72PDZ-1G1__图片预览
型号: MT18JDF1G72PDZ-1G1__
PDF下载: 下载PDF文件 查看货源
内容描述: 8GB ( X72 , ECC , DR ) 240针DDR3 VLP RDIMM特点 [8GB (x72, ECC, DR) 240-Pin DDR3 VLP RDIMM Features]
分类和应用: 双倍数据速率
文件页数/大小: 19 页 / 388 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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8GB (x72, ECC, DR) 240-Pin DDR3 VLP RDIMM  
Electrical Specifications  
Electrical Specifications  
Stresses greater than those listed may cause permanent damage to the module. This is a  
stress rating only, and functional operation of the module at these or any other condi-  
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-  
solute maximum rating conditions for extended periods may adversely affect reliability.  
Table 8: Absolute Maximum Ratings  
Symbol  
VDD  
Parameter  
Min  
–0.4  
–0.4  
Max  
1.975  
1.975  
Units  
VDD supply voltage relative to VSS  
Voltage on any pin relative to VSS  
V
V
VIN, VOUT  
Table 9: Operating Conditions  
Symbol Parameter  
Min  
1.425  
–600  
Nom  
1.5  
Max  
1.575  
600  
Units Notes  
VDD  
IVTT  
VDD supply voltage  
V
Termination reference current from  
VTT  
mA  
VTT  
II  
Termination reference voltage (DC) –  
command/address bus  
0.49 × VDD - 20mV  
0.5 × VDD 0.51 × VDD + 20mV  
V
1
5
Input leakage current; Address in-  
µA  
Any input 0V VIN  
puts, RAS#,  
VDD; VREF input 0V VIN CAS#, WE#,  
0.95V (All other pins S#, CKE, ODT,  
not under test = 0V)  
BA, CK, CK#  
DM  
–4  
0
0
4
IOZ  
Output leakage current; DQ, DQS,  
–10  
10  
µA  
µA  
0V VOUT VDD; DQ  
and ODT are disabled;  
ODT is HIGH  
DQS#  
IVREF  
VREF supply leakage current;  
–18  
0
18  
VREFDQ = VDD/2 or VREFCA = VDD/2  
(All other pins not under test = 0V)  
TA  
TC  
Module ambient  
operating temperature  
Commercial  
0
0
70  
95  
°C  
°C  
2, 3  
DDR3 SDRAM compo-  
nent case operating  
temperature  
Commercial  
2, 3, 4  
1. VTT termination voltage in excess of the stated limit will adversely affect the command  
and address signals’ voltage margin and will reduce timing margins.  
Notes:  
2. TA and TC are simultaneous requirements.  
3. For further information, refer to technical note TN-00-08: “Thermal Applications,”  
available on Micron’s Web site.  
4. The refresh rate is required to double when 85°C < TC 95°C.  
5. Inputs are terminated to VDD/2. Input current is dependent on terminating resistance se-  
lected in register.  
PDF: 09005aef8482a8a7  
jdf18c1gx72pdz.pdf – Rev. D 12/12 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
12  
© 2011 Micron Technology, Inc. All rights reserved.