256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
140.6µs (256MB) or 70.3µs (512MB, 1GB, 2GB);
burst refreshing or posting by the DRAM control-
ler greater than eight refresh cycles is not allowed.
22. The valid data window is derived by achieving
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
m aintain at least the target DC level, VIL (DC)
or VIH (DC).
t
other specifications: tHP (tCK/ 2), tDQSQ, and QH
26. JEDEC specifies CK and CK# input slew rate must
be ≥ 1V/ ns (2V/ ns differentially).
(tQH = tHP - tQHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/ 55, beyond which functionality is
uncertain. Figure 8, Derating Data Valid Window
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/ DQS slew rate is less than 0.5V/ ns, tim ing
t
must be derated: 50ps must be added to DS and
tDH for each 100mv/ ns reduction in slew rate. If
slew rate exceeds 4V/ ns, functionality is uncer-
tain.
t
tHP - QHS, shows derating curves for duty cycles
ranging between 50/ 50 and 45/ 55.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
28. VDD m ust not vary m ore than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to ±150ps of jitter. Each
tim ing param eter is allowed to vary by the sam e
amount.
t
t
25. To maintain a valid level, the transitioning edge of
the input must:
30. tHP m in is the lesser of CL m inim um and CH
m inim um actually applied to the device CK and
CK# inputs, collectively during bank active.
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL (AC)
or VIH (AC).
Fig u re 8: De ra t in g Da t a Va lid Win d o w
tHP - tQHS
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
-262/-26A/-265 @ tCK = 10ns
-262/-26A/-265 @ tCK = 7.5ns
-335 @ tCK = 6ns
NA
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
Clock Duty Cycle
47/53
46.5/54.5
46/54
45.5/55.5
45/55
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
21
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