256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 15: IDD Sp e cifica t io n s a n d Co n d it io n s – 2GB
DDR SDRAM Components only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2VV
MAX
-26A/
-265
PARAMETER/CONDITION
SYM
-335
-262
UNITS NOTES
IDD0a
OPERATING CURRENT: One device bank; Active-Precharge; tRC =
1,080
1,080
1,240
mA
20, 42
t
tRC (MIN); tCK = CK (MIN); DQ, DM and DQS inputs changing once
per clock cyle; Address and control inputs changing once every two
clock cycles
IDD1a
1,320
1,320
1,520
mA
20, 42
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
IDD2Pb
IDD2Fb
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
80
80
160
960
mA
mA
21, 28,
44
t
idle; Power-down mode; tCK = CK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =
720
720
45
tCK MIN; CKE = HIGH; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS, and DM
IDD3Pb
IDD3Nb
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
560
720
560
720
480
720
mA
mA
21, 28,
44
t
active; Power-down mode; tCK = CK (MIN); CKE = LOW
40
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM
andDQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
IDD4Ra
1,360
1,280
1,360
1,280
1,680
1,760
mA
mA
20, 42
20
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
t
cycle; tCK = CK (MIN); IOUT = 0mA
IDD4Wa
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
t
clock cycle; tCK = CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
IDD5b
tREFC = tRFC (MIN)
AUTO REFRESH CURRENT
4,640
160
4,640
160
5,280
160
mA
mA
20, 44
20, 44
IDD5Ab
tREFC = 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
IDD6b
IDD7a
80
80
144
mA
mA
9
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge, tRC = tRC (MIN); tCK = CK (MIN); Address and
3,280
3,240
3,960
20, 43
t
control inputs change only during Active READ, or WRITE
commands
NOTE:
a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode.
b: Value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
17
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