256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 22: Se ria l Pre se n ce -De t e ct Ma t rix (256MB, 512MB, a n d 1GB) (Co n t in u e d )
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31
BYTE
DESCRIPTION
ENTRY (VERSION) MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A
94
Variable Data
Variable Data
–
Variable Data
Variable Data
–
Variable Data
Variable Data
–
Week of Manufacture in BCD
Module Serial Number
95-98
99-127
Manufacturer-Specific Data (RSVD)
NOTE:
1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.
t
t
2. The value of RAS used for -26A/-265 modules is calculated from RC - tRP. Actual device spec. value is 40 ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is
represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.
t
t
4. The value of RP, tRCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR
SDRAM device specification is 15ns.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
31
MICRON [ MICRON TECHNOLOGY ]
