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MT16VDDT3264AG-335 参数 Datasheet PDF下载

MT16VDDT3264AG-335图片预览
型号: MT16VDDT3264AG-335
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR SDRAM UNBUFFERED DIMM]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 35 页 / 875 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第26页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第27页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第28页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第29页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第31页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第32页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第33页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第34页  
256MB, 512MB, 1GB, 2GB (x64, DR)  
184-PIN DDR SDRAM UDIMM  
Ta b le 22: Se ria l Pre se n ce -De t e ct Ma t rix (256MB, 512MB, a n d 1GB) (Co n t in u e d )  
“1”/0”: Serial Data, “driven to HIGH/driven to LOW”; notes appear on page 31  
BYTE  
DESCRIPTION  
ENTRY (VERSION) MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A  
28  
12ns (-335)  
15ns (-262/-26A/-265)  
30  
3C  
30  
3C  
30  
3C  
Minimum Row Active to Row Active,  
tRRD  
Minimum Ras# to CAS# Delay, tRCD  
(see note 4)  
29  
30  
18ns (-335)  
15ns (-262)  
20ns (-26A/-265)  
48  
3C  
50  
48  
3C  
50  
48  
3C  
50  
t
42ns (-335)  
45ns (-262/-26A/-265)  
2A  
2D  
2A  
2D  
2A  
2D  
Minimum RAS# Pulse Width, RAS,  
(see note 2)  
31  
32  
128MB, 256MB,  
512MB  
20  
40  
80  
Module Rank Density  
0.8ns (-335)  
1.0ns (-262-26A/-265)  
80  
A0  
80  
A0  
80  
A0  
Address and Command Setup Time,  
tIS, (see note 3)  
33  
34  
35  
0.8ns (-335)  
1.0ns (-262/-26A/-265)  
80  
A0  
80  
A0  
80  
A0  
Address and Command Hold Time,  
tIH, (see note 3)  
Data/Data Mask Input Setup Time,  
tDS  
0.45ns (-335)  
0.5ns (-262/-26A/-265)  
45  
50  
45  
50  
45  
50  
0.45ns (-335)  
0.5ns (-262/-26A/-265)  
45  
50  
45  
50  
45  
50  
Data/Data Mask Input  
t
Hold Time, DH  
36-40  
41  
00  
00  
00  
Reserved  
Min Active Auto Refresh Time, tRC  
60ns (-335/-262)  
65ns (-26A/-265)  
3C  
41  
3C  
41  
3C  
41  
42  
43  
44  
45  
72ns (-335)  
75ns (-262/-26A/-265)  
48  
4B  
48  
4B  
48  
4B  
Minimum Auto Refresh to Active/  
t
Auto Refresh Command Period, RFC  
SDRAM Device Max Cycle Time,  
tCKMAX  
12ns (-335)  
13ns (-262/-26A/-265)  
30  
34  
30  
34  
30  
34  
0.45ns (-335)  
0.5ns (-262/-26A/-265)  
2D  
32  
2D  
32  
2D  
32  
SDRAM Device Max DQS-DQ Skew  
t
Time, DQSQ  
0.55ns (-335)  
0.75ns (-262/-26A/-265)  
55  
75  
55  
75  
55  
75  
SDRAM Device Max Read Data Hold  
t
Skew Factor, QHS  
46-61 Reserved  
00  
01/11  
00  
00  
01/11  
00  
00  
01/11  
00  
47  
DIMM Height  
Standard/Low-Profile  
Release 1.0  
46-61 Reserved  
62  
63  
SPD Revision  
10  
10  
10  
Checksum For Bytes 0-62  
-335  
-262  
-26A  
-265  
05/15  
98/A8  
C5/D5  
F5/05  
28/38  
BB/CB  
E8/F8  
18/28  
69/79  
FC/0C  
29/39  
59/69  
64  
65-71  
72  
MICRON  
(Continued)  
01–12  
2C  
FF  
2C  
FF  
2C  
FF  
Manufacturers JEDEC ID Code  
Manufacturers JEDEC ID Code  
Manufacturing Location  
01–0C  
01–0C  
01–0C  
73-90  
91  
Variable Data  
Variable Data  
00  
Variable Data  
Variable Data  
00  
Variable Data  
Variable Data  
00  
Module Part Number (ASCII)  
PCB Identification Code  
92  
0
Identification Code (Continued)  
Year of Manufacture in BCD  
93  
Variable Data  
Variable Data  
Variable Data  
pdf: 09005aef80739fa5, source: 09005aef807397e5  
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2004 Micron Technology, Inc.  
30  
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