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MT16VDDT3264AG-335 参数 Datasheet PDF下载

MT16VDDT3264AG-335图片预览
型号: MT16VDDT3264AG-335
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR SDRAM UNBUFFERED DIMM]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 35 页 / 875 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第15页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第16页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第17页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第18页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第20页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第21页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第22页浏览型号MT16VDDT3264AG-335的Datasheet PDF文件第23页  
256MB, 512MB, 1GB, 2GB (x64, DR)  
184-PIN DDR SDRAM UDIMM  
Ta b le 17: DDR SDRAM Co m p o n e n t Ele ct rica l Ch a ra ct e rist ics a n d Re co m m e n d e d  
AC Op e ra t in g Co n d it io n s (Co n t in u e d )  
Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C TA +70°C; VDD = VDDQ = +2.5V ±0.2V  
AC CHARACTERISTICS  
PARAMETER  
-335  
-262  
-26A/-265  
MIN MAX UNITS NOTES  
SYMBOL MIN  
MAX  
MIN  
MAX  
tISS  
0.80  
2.2  
12  
1
1
ns  
12  
Address and control input setup time (slow slew  
rate)  
tIPW  
2.2  
2.2  
ns  
Address and Control input pulse width (for  
each input)  
tMRD  
tQH  
LOAD MODE REGISTER command cycle time  
15  
15  
ns  
ns  
tHP -  
tQHS  
tHP -  
tQHS  
tHP -  
tQHS  
22, 23  
31, 49  
DQ-DQS hold, DQS to first DQ to go non-valid,  
per access  
tQHS  
tRAS  
0.55  
0.75  
0.75  
ns  
ns  
ns  
Data hold skew factor  
42  
15  
70,000  
40  
15  
120,000  
40  
20  
120,000  
ACTIVE to PRECHARGE command  
ACTIVE to READ with Auto precharge  
command  
tRAP  
tRC  
60  
75  
60  
75  
65  
75  
ns  
ns  
ACTIVE to ACTIVE/AUTO REFRESH command  
period  
44  
AUTO REFRESH command period 256MB,  
512MB, 1GB  
tRFC  
2GB  
120  
15  
120  
15  
120  
20  
ns  
ns  
tRCD  
tRP  
tRPRE  
tRPST  
tRRD  
tWPRE  
tWPRES  
tWPST  
tWR  
tWTR  
na  
ACTIVE to READ or WRITE delay  
15  
0.9  
0.4  
12  
0.25  
0
15  
0.9  
0.4  
15  
0.25  
0
20  
0.9  
0.4  
15  
ns  
PRECHARGE command period  
DQS read preamble  
tCK  
tCK  
ns  
1.1  
0.6  
1.1  
0.6  
1.1  
0.6  
38  
38  
DQS read postamble  
ACTIVE bank a to ACTIVE bank b command  
DQS write preamble  
tCK  
ns  
0.25  
0
DQS write preamble setup time  
DQS write postamble  
18, 19  
17  
tCK  
ns  
0.4  
15  
1
0.6  
0.4  
15  
1
0.6  
0.4  
15  
0.6  
Write recovery time  
tCK  
ns  
Internal WRITE to READ command delay  
Data valid output window  
1
tQH -tDQSQ  
140.6  
tQH -tDQSQ  
140.6  
tQH -tDQSQ  
140.6  
22  
µs  
µs  
21  
21  
REFRESH to REFRESH command  
interval  
256MB  
tREFC  
tREFI  
70.3  
70.3  
70.3  
512MB, 1GB,  
2GB  
15.6  
7.8  
15.6  
7.8  
15.6  
7.8  
µs  
µs  
21  
21  
Average periodic refresh interval 256MB  
512MB, 1GB,  
2GB  
tVTD  
tXSNR  
tXSRD  
Terminating voltage delay to VDD  
0
0
0
ns  
ns  
75  
75  
75  
Exit SELF REFRESH to non-READ command  
Exit SELF REFRESH to READ command  
tCK  
200  
200  
200  
pdf: 09005aef80739fa5, source: 09005aef807397e5  
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2004 Micron Technology, Inc.  
19  
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