256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 16: Ca p a cit a n ce
Note: 11; notes appear on pages 20–23
PARAMETER
SYMBOL
MIN MAX
UNITS
CIO
CI1
CI1
CI2
CI3
8
10
48
24
15
18
pF
pF
pF
pF
pF
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: S#, CKE
32
16
11
12
Input Capacitance: CK0, CK0#
Input Capacitance: CK1, CK1#; CK2, CK2#
Ta b le 17: DDR SDRAM Co m p o n e n t Ele ct rica l Ch a ra ct e rist ics a n d Re co m m e n d e d
AC Op e ra t in g Co n d it io n s
Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS
PARAMETER
-335
-262
MIN MAX
-0.75 +0.75 -0.75 +0.75
-26A/-265
SYMBOL MIN
MAX
MIN MAX UNITS NOTES
tAC
-0.7
+0.7
ns
Access window of DQs from CK/
CK#
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tCK
tCK
ns
0.45
0.45
6
0.55
0.55
13
0.45
0.45
7.5
0.55
0.55
13
0.45
0.45
7.5
0.55
0.55
13
26
CK high-level width
CK low-level width
Clock cycle time
26
CL = 2.5
CL = 2
41, 46
41, 46
23, 27
23, 27
27
7.5
13
7.5/10
0.5
13
7.5/10
0.5
13
ns
ns
ns
ns
ns
0.45
0.45
1.75
-0.60
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
0.5
0.5
1.75
1.75
+0.60 -0.75 +0.75 -0.75 +0.75
Access window of DQS from CK/
CK#
tDQSH
tDQSL
tDQSQ
tCK
tCK
ns
0.35
0.35
0.35
0.35
0.35
0.35
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
0.45
1.25
0.5
0.5
22, 23
tDQSS
tDSS
tCK
tCK
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
Write command to first DQS latching transition
DQS falling edge to CK rising -
setup time
tDSH
tCK
0.2
0.2
0.2
DQS falling edge from CK rising -
hold time
tHP
tHZ
tLZ
tCH,tCL
+0.70
tCH,tCL
+0.75
tCH,tCL
+0.75
ns
ns
ns
ns
31
Half clock period
16, 37
16, 37
12
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
-0.70
0.75
-0.75
0.90
-0.75
.90
tIHF
Address and control input hold time (fast slew
rate)
tISF
Address and control input setup time (fast slew
rate)
0.75
0.80
0.90
1
.90
1
ns
ns
12
12
tIHS
Address and control input hold time (slow slew
rate)
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
18
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