512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202)
Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD = VDDQ = +2.5V 0.2V
AC CHARACTERISTICS
-26A
-265
-202
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
tAC
tCH
tCL
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
ns
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
tCK
tCK
ns
0.45
0.45
7.5
0.55
0.55
13
0.45
0.45
7.5
0.55 0.45 0.55
0.55 0.45 0.55
26
26
tCK (2.5)
tCK (2)
tDH
13
13
8
13
13
40, 46
40, 46
23, 27
23, 27
27
CL=2.5
CL=2
7.5
13
10
10
0.6
0.6
2
ns
ns
ns
ns
ns
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
0.5
0.5
tDS
0.5
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
1.75
1.75
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
tCK
tCK
0.35
0.35
0.35
0.35
0.35
0.35
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
0.5
0.5
0.6
ns
22, 23
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tCK
tCK
tCK
0.75
0.20
0.20
1.25
0.75
0.20
0.20
1.25 0.75 1.25
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.20
0.20
tCH,tCL
+0.75
tCH,tCL
+0.75
tCH,tCL
+0.8
ns
8
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
ns
ns
ns
16, 37
16, 38
12
-0.75
0.90
-0.75
0.90
-0.8
tIHF
1.1
Address and control input hold time (fast slew
rate)
tISF
tIHS
tISS
.900
1
0.90
1
1.1
1.1
1.1
ns
ns
ns
12
12
12
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
1
1
Address and control input setup time (slow slew
rate)
tIPW
2.2
2.2
2.2
ns
Address and Control input pulse width (for each
input)
tMRD
tQH
LOAD MODE REGISTER command cycle time
15
15
16
ns
ns
tHP -tQHS
0.75
tHP -tQHS
0.75
tHP -tQHS
1
22, 23
31
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tQHS
tRAS
tRAP
tRC
Data hold skew factor
ns
40 120,000 40 120,000 40 120,000 ns
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
20
65
20
65
20
70
ns
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
tRFC
tRCD
tRP
75
20
20
75
20
20
80
20
20
ns
ns
ns
44
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18
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