256MB / 512MB (x64)
168-PIN SDRAM DIMMs
Ge n e ra l De scrip t io n
The MT8LSDT13264A(I) and MT16LSDT6464A(I)
are high-speed CMOS, dynam ic random -access,
256MB and 512MB memory modules organized in x64
configurations. These m odules use internally config-
ured quad-bank SDRAMS with a synchronous inter-
face (all signals are registered on the positive edge of
the clock signals CK0-CK3).
Se ria l Pre se n ce -De t e ct Op e ra t io n
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
gram m ed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/ WRITE operations
between the m aster (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/ EEPROM addresses.
Read and write accesses to the SDRAM modules are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank; A0–A12
select the device row). The address bits registered
coincident with the READ or WRITE command are
used to select the starting column location for the
burst access.
The m odules provide for program m able READ or
WRITE burst length of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An AUTO PRE-
CHARGE function may be enabled to provide a self-
tim ed row precharge that is initiateda the end of the
burst sequence.
The m odules use an internal pipelined architecture
to achieve high-speed operation. This architecture is
com patible with the 2n rule of prefetch architectures,
but it also allows the column address to be changed on
every clock cycle to achieve a high-speed, fully random
access. Precharging one device bank while accessing
one of the other three device banks will hide the pre-
charge cycles and provide seamless, high-speed, ran-
dom-access operation.
The modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAM Fu n ct io n a l De scrip t io n
In general, the 256Mb SDRAMs are quad-bank
DRAMs that operate at 3.3V and include a synchro-
nous interface (all signals are registered on the positive
edge of the clock signal, CLK). The four banks of the x8
configured devices used for these m odules are config-
ured as 8,192 bit-rows by 1,024 bit-columns, by 8
input/ output bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE comm and, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the active command are
used to select the device bank and row to be accessed;
BA0 and BA1 select the device bank, A0–A12 select the
device row. The address bits A0–A9 registered coinci-
dent with the READ or WRITE com m and are used to
select the starting device colum n location for the burst
access.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation covering device initialization, register
definition, com m and descriptions and device opera-
tion.
SDRAM modules offer substantial advances in
DRAM operating performance, including the ability to
syncronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between intenal banks in order to hide precharge
tim e and the capability to random ly change colum n
addresses on each clock cycle during a burst access.
For more information regarding SDRAM operation,
refer to the 256Mb SDRAM component data sheet.
In it ia liza t io n
SDRAMS must be powered up and initialized in a
predefined m anner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to VDD and VDDQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within tim ing constrants specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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MICRON [ MICRON TECHNOLOGY ]
