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MT16LSDF3264LHY-10E 参数 Datasheet PDF下载

MT16LSDF3264LHY-10E图片预览
型号: MT16LSDF3264LHY-10E
PDF下载: 下载PDF文件 查看货源
内容描述: [SMALL-OUTLINE SDRAM MODULE]
分类和应用: 动态存储器
文件页数/大小: 22 页 / 476 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256MB, 512MB (x64, DR)  
144-PIN SDRAM SODIMM  
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions  
All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V  
PARAMETER/CONDITION  
SYMBOL  
MIN  
MAX  
UNITS  
VDD  
VIH  
VIL  
VOL  
ILI  
3
3.6  
V
V
Supply voltage  
VDD × 0.7 VDD × 0.5  
Input high voltage: Logic 1; All inputs  
–1  
VDD × 0.3  
V
Input low voltage: Logic 0; All inputs  
0.4  
10  
10  
30  
2
V
Output low voltage: IOUT = 3mA  
µA  
µA  
µA  
mA  
Input leakage current: VIN = GND to VDD  
Output leakage current: VOUT = GND to VDD  
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10%  
Power supply current: SCL clock frequency = 100 KHz  
ILO  
ISB  
ICC  
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions  
All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V  
PARAMETER/CONDITION  
SYMBOL  
MIN MAX UNITS  
NOTES  
tAA  
tBUF  
0.2  
1.3  
0.9  
µs  
µs  
1
SCL LOW to SDA data-out valid  
Time the bus must be free before a new transition can start  
Data-out hold time  
tDH  
200  
ns  
tF  
300  
ns  
2
SDA and SCL fall time  
tHD:DAT  
tHD:STA  
tHIGH  
tI  
tLOW  
tR  
fSCL  
tSU:DAT  
tSU:STA  
tSU:STO  
tWRC  
0
µs  
Data-in hold time  
0.6  
0.6  
µs  
Start condition hold time  
Clock HIGH period  
µs  
50  
ns  
Noise suppression time constant at SCL, SDA inputs  
Clock LOW period  
1.3  
µs  
0.3  
µs  
2
SDA and SCL rise time  
400  
KHz  
ns  
SCL clock frequency  
100  
0.6  
0.6  
Data-in setup time  
µs  
3
4
Start condition setup time  
Stop condition setup time  
WRITE cycle time  
µs  
10  
ms  
NOTE:  
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising  
edge of SDA.  
2. This parameter is sampled.  
3. For a restart condition, or following a WRITE cycle.  
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of  
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA  
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.  
pdf: 09005aef807924d2, source: 09005aef807924f1  
SDF16C32_64x64HG.fm - Rev. E 4/06 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2006 Micron Technology, Inc. All rights reserved.  
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