8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
GENERAL DESCRIPTION
The Micron
®
MT8LD864A X, MT16LD1664A X
and MT32LD3264A X are randomly accessed 64MB,
128MB and 256MB memories organized in a x64 con-
figuration. They are specially processed to operate
from 3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22/23 address bits, which are
entered 12 bits (A0-A11) at RAS# time and 11/12 bits
(A0-A11) at CAS# time.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE oc-
curs when WE# falls after CAS# was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of OE#. During
LATE WRITE or READ-MODIFY-WRITE cycles, OE#
must be taken HIGH to disable the data-outputs prior
to applying input data. If a LATE WRITE or READ-
MODIFY-WRITE is attempted while keeping OE# LOW,
no WRITE will occur, and the data-outputs will drive
read data from the accessed location.
toggle from valid data to High-Z and back to the same
valid data. If OE# is toggled or pulsed after CAS# goes
HIGH while RAS# remains LOW, data will transition
to and remain High-Z.
During an application, if the DQ outputs are wire
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also tristate the outputs. Inde-
pendent of OE# control, the outputs will disable after
t
OFF, which is referenced from the rising edge of RAS#
or CAS#, whichever occurs last. (Refer to the 16 Meg x
4 [MT4LC16M4H9] DRAM data sheet for additional
information on EDO functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and ex-
ecuting any RAS# cycle (READ, WRITE) or RAS# RE-
FRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (A0-A10/A11) are
executed at least every
t
REF, regardless of sequence. The
CBR REFRESH cycle will invoke the internal refresh
counter for automatic RAS# addressing.
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGE-
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back
HIGH. EDO provides for CAS# precharge time (
t
CP) to
occur without the output data going invalid. This
elimination of CAS# output control provides for pipe-
line READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE#
is pulsed while RAS# and CAS# are LOW, data will
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide 8 unique DIMM/EEPROM
addresses.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
