4GB, 8GB (x64, DR) 204-Pin 1.35V DDR3L SODIMM
Serial Presence-Detect EEPROM
Serial Presence-Detect EEPROM
For the latest SPD data, refer to Micron's SPD page: micron.com/spd.
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VDDSPD
Parameter/Condition
Symbol
VDDSPD
VIL
Min
Max
3.6
Units
V
Supply voltage
3.0
–0.45
VDDSPD x 0.7
–
Input low voltage: Logic 0; All inputs
Input high voltage: Logic 1; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
VDDSPD x 0.3
VDDSPD + 1.0
0.4
V
VIH
V
VOL
V
ILI
0.1
2.0
µA
µA
ILO
0.05
2.0
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
Clock frequency
Symbol
tSCL
tHIGH
tLOW
Min
10
Max
400
–
Units
kHz
µs
Notes
Clock pulse width HIGH time
Clock pulse width LOW time
SDA rise time
0.6
1.3
–
–
µs
tR
tF
300
300
–
µs
1
1
SDA fall time
20
ns
Data-in setup time
tSU:DAT
tHD:DI
tHD:DAT
tAA:DAT
tSU:STA
tHD:STA
tSU:STO
tBUF
100
0
ns
Data-in hold time
–
µs
Data-out hold time
200
0.2
0.6
0.6
0.6
1.3
900
0.9
–
ns
Data out access time from SCL LOW
Start condition setup time
Start condition hold time
Stop condition setup time
µs
2
3
µs
–
µs
–
µs
Time the bus must be free before a new transition can
start
–
µs
WRITE time
tW
–
10
ms
1. Guaranteed by design and characterization, not necessarily tested.
Notes:
2. To avoid spurious start and stop conditions, a minimum delay is placed between the fall-
ing edge of SCL and the falling or rising edge of SDA.
3. For a restart condition, or following a WRITE cycle.
PDF: 09005aef846206a0
ktf16c512_1gx64hz.pdf - Rev. K 7/15 EN
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19
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