512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
General Description
General Description
The MT16HTF6464A, MT16HTF12864A, and MT16HTF25664A DDR2 SDRAM modules
are high-speed, CMOS, dynamic random-access 512MB, 1GB, and 2GB memory
modules organized in x64 configuration. DDR2 modules use internally configured 4-
bank (512MB, 1GB) or 8-bank (2GB) DDR2 devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DDR2 device core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 device
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs.
DDR2 modules operate from a differential clock (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands
(address and control signals) are registered at every positive edge of CK. Input data is
registered on both edges of DQS, and output data is referenced to both edges of DQS, as
well as to both edges of CK.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various DDR2 organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/WRITE operations between the
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master (system logic) and the slave EEPROM device occur via a standard I C bus using
the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide
eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the
module, permanently disabling hardware write protect.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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©2003 Micron Technology, Inc. All rights reserved.
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