512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
Figure 4:
Data Validity
SCL
SDA
Data stable
Data change
Data stable
Figure 5:
Definition of Start and Stop
SCL
SDA
Start
bit
Stop
bit
Figure 6:
Acknowledge Response From Receiver
((
))
SCL from master
((
))
Data output
from transmitter
((
))
((
))
Data output
from receiver
Acknowledge
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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