OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
RAS#-ONLY REFRESH CYCLE
(WE# = DON’T CARE)
t
RC
t
t
RP
RAS
V
IH
RAS#
CAS#
V
IL
t
t
CRP
RPC
V
V
IH
IL
t
t
RAH
ASR
V
V
IH
IL
ADDR
DQ
ROW
ROW
V
OH
OL
OPEN
V
CBR REFRESH CYCLE
(Addresses = DON’T CARE)
t
t
t
t
RAS
RP
RAS
RP
V
V
IH
IL
RAS#
t
t
RPC
CP
t
t
t
RPC
t
t
CHR
CSR
CHR
CSR
V
V
IH
IL
CAS#
DQ
V
V
OH
OL
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-6
SYMBOL
MIN
0
MAX
UNITS
ns
SYMBOL
MIN
MAX
UNITS
ns
t
t
ASR
RAS
60
110
40
0
10,000
t
t
CHR
15
10
10
10
10
ns
RC
ns
t
t
CP
ns
RP
ns
t
t
CRP
ns
RPC
ns
t
t
CSR
ns
WRH
10
10
ns
t
t
RAH
ns
WRP
ns
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
14
MICRON [ MICRON TECHNOLOGY ]
