OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
FAST-PAGE-MODE EARLY-WRITE CYCLE
t
t
RP
RASP
V
IH
RAS#
CAS#
V
IL
t
t
t
t
t
CSH
PC
CP
RSH
CAS
t
t
t
t
t
t
CP
CRP
RCD
CAS
CAS
CP
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
t
t
t
t
t
CWL
CWL
WCH
WP
CWL
WCH
WP
t
t
t
t
t
WCS
WCS
WCH
WP
WCS
V
V
IH
IL
WE#
DQ
t
t
t
WCR
DH
RWL
t
t
t
t
t
DS
DS
DH
DS
DH
V
IOH
IOL
VALID DATA
VALID DATA
VALID DATA
V
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-6
SYMBOL
MIN
45
0
MAX
UNITS
ns
SYMBOL
MIN
15
10
60
20
40
15
15
10
45
0
MAX
UNITS
ns
t
t
AR
RAD
t
t
ASC
ns
RAH
ns
t
t
ASR
0
ns
RASP
125,000
ns
t
t
CAH
10
15
10
10
60
15
10
0
ns
RCD
ns
t
t
CAS
10,000
ns
RP
ns
t
t
CP
ns
RSH
ns
t
t
CRP
ns
RWL
ns
t
t
CSH
ns
WCH
ns
t
t
CWL
ns
WCR
ns
t
t
DH
ns
WCS
ns
t
t
DS
ns
WP
10
ns
t
PC
35
ns
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
12
MICRON [ MICRON TECHNOLOGY ]
