OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
FAST-PAGE-MODE READ CYCLE
t
t
RASP
RP
V
IH
RAS#
CAS#
V
IL
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
AR
t
t
t
RAD
RAH
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
WE#
ROW
COLUMN
COLUMN
t
COLUMN
t
ROW
t
RRH
RCS
t
RCS
t
t
RCH
RCS
t
RCH
RCH
V
V
IH
IL
t
t
t
t
t
t
t
t
t
AA
AA
AA
RAC
CAC
CPA
CAC
CPA
CAC
t
t
OFF
OFF
t
OFF
t
t
t
CLZ
CLZ
CLZ
V
V
IOH
IOL
VALID
DATA
VALID
DATA
VALID
DATA
DQ
OPEN
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-6
SYMBOL
MIN
MAX
UNITS
SYMBOL
MIN
3
MAX
UNITS
ns
t
t
AA
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OFF
15
t
t
AR
45
0
PC
35
ns
t
t
ASC
RAC
60
ns
t
t
ASR
0
RAD
15
10
60
20
0
ns
t
t
CAC
15
RAH
ns
t
t
CAH
10
15
3
RASP
125,000
ns
t
t
CAS
10,000
RCD
ns
t
t
CLZ
RCH
ns
t
t
CP
10
RCS
0
ns
t
t
CPA
35
RP
40
0
ns
t
t
CRP
10
60
RRH
ns
t
t
CSH
RSH
15
ns
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
11
MICRON [ MICRON TECHNOLOGY ]
