DC and AC parameters
Table 20. Synchronous burst read AC characteristics(1)
Symbol Parameter Test condition
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
M58BW016
Unit
70
80
t
Address Valid to Latch Enable Low
E = V
Min
Min
0
0
ns
ns
AVLL
IL
Burst Address Advance High to Valid
Clock Edge
t
E = V , G = V , L = V
8
8
8
BHKH
IL
IL
IH
IH
Burst Address Advance Low to Valid
Clock Edge
t
E = V , G = V , L = V
Min
Min
8
0
ns
BLKH
IL
IL
t
Chip Enable Low to Latch Enable Low
Output Enable Low to Output Valid
0
ns
ns
ELLL
t
E = V , L = V
IH
Min 25
25
GLQV
IL
Valid Clock Edge to Address
Transition
t
t
E = V
E = V
E = V
Min
Min
Min
5
0
0
5
0
0
ns
ns
ns
KHAX
IL
IL
IL
t
Valid Clock Edge to Latch Enable Low
KHLL
Valid Clock Edge to Latch Enable
Transition
KHLX
E = V , M58BW016DT/B Min
3
3
3
3
ns
ns
IL
t
Valid Clock Edge to Output Transition G = V ,
KHQX
IL
M58BW016FT/B Min
L = V
IH
M58BW016DT/B Min
M58BW016FT/B Min
6
5
6
6
5
6
ns
ns
ns
t
Latch Enable Low to Valid Clock Edge E = V
IL
LLKH
(2)
t
Output Valid to Valid Clock Edge
E = V , G = V , L = V
Min
Min
QVKH
IL
IL
IH
IH
IH
Valid Data Ready Low to Valid Clock
Edge
t
E = V , G = V , L = V
6
6
ns
ns
RLKH
IL
IL
t
Valid Clock Edge to Output Valid
E = V , G = V , L = V
Max 11
11
KHQV
IL
IL
1. For other timings see Table 16: Asynchronous bus read AC characteristics.
2. Data output should be read on the valid clock edge.
Figure 14. Synchronous burst read (data valid from ‘n’ clock rising edge)
n
n+1
n+2
n+3
n+4
n+5
K
tKHQV
tQVKH
DQ0-DQ31
Q0
Q1
Q2
Q3
Q4
Q5
tKHQX
SETUP
Burst Read
Q0 to Q3
Note: n depends on Burst X-Latency
AI04408b
1. For set up signals and timings see synchronous burst read.
48/70
MICRON [ MICRON TECHNOLOGY ]
