Status register
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
5
Status register
The Status register provides information on the current or previous program or erase
operation. The various bits in the status register convey information and errors on the
operation. They are output on DQ7-DQ0.
To read the status register the Read Status Register command can be issued. The status
register is automatically read after Program, Erase or Program/Erase Resume commands.
The status register can be read from any address.
The contents of the status register can be updated during an erase or program operation by
toggling the Output Enable or Output Disable pins or by deactivating (Chip Enable, VIH) and
then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, VIH.) the device.
The status register bits are summarized in Table 11: Status register bits. Refer to Table 11 in
conjunction with the following text descriptions.
5.1
Program/erase controller status (bit 7)
The Program/erase controller status bit indicates whether the program/erase controller is
active or inactive. When the program/erase controller status bit is set to ‘0’, the
program/erase controller is active; when bit7 is set to ‘1’, the program/erase controller is
inactive.
The program/erase controller status is set to ‘0’ immediately after a Program/Erase
Suspend command is issued until the program/erase controller pauses. After the
program/erase controller pauses the bit is set to ‘1’.
During program and erase operations the program/erase controller status bit can be polled
to find the end of the operation. The other bits in the status register should not be tested until
the program/erase controller completes the operation and the bit is set to ‘1’.
After the program/erase controller completes its operation the erase status (bit5), program
status bits should be tested for errors.
5.2
Erase suspend status (bit 6)
The erase suspend status bit indicates that an erase operation has been suspended and is
waiting to be resumed. The erase suspend status should only be considered valid when the
program/erase controller status bit is set to ‘1’ (program/erase controller inactive); after a
Program/Erase Suspend command is issued the memory may still complete the operation
rather than entering the suspend mode.
When the erase suspend status bit is set to ‘0’, the program/erase controller is active or has
completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has
been issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued the erase suspend status bit returns to
‘0’.
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