Command interface
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
4.10
Set Burst Configuration Register command
The Set Burst Configuration Register command is used to write a new value to the burst
configuration control register which defines the burst length, type, X and Y latencies,
synchronous/asynchronous read mode and the valid clock edge configuration.
Two bus write cycles are required to issue the Set Burst Configuration Register command.
The first cycle writes the setup command and the address corresponding to the set burst
configuration register content. The second cycle writes the burst configuration register data
and the confirm command. Once the command is issued the memory returns to read mode
as if a Read Memory Array command had been issued.
The value for the burst configuration register is always presented on A0-A15. M0 is on A0,
M1 on A1, etc.; the other address bits are ignored.
Table 9.
Commands(1)
Bus operations
Command
1st cycle
2nd cycle
Op.
Addr.
Data
Op.
Addr.
Data
Read Memory Array
≥ 2
≥ 2
Write
X
FFh
Read
RA
RD
Read Electronic Signature
(manufacturer code)
Write
Write
Write
X
X
X
90h
90h
90h
Read
Read
Read
00000h
00001h
00005h
20h
IDh
Read Electronic Signature
(device code)
≥ 2
≥ 2
Read Electronic Signature
(burst configuration register)
BCRh
Read Status Register
Read Query
2
≥ 2
1
Write
Write
Write
Write
X
X
X
X
70h
98h
50h
20h
Read
Read
X
SRDh
QDh
QAh
Clear Status Register
Block Erase
2
Write
Write
BAh
PA
D0h
PD
40h
10h
Program
2
Write
X
Program/Erase Suspend
Program/Erase Resume
1
1
2
Write
Write
Write
X
X
X
B0h
D0h
60h
Set Burst Configuration Register
Write
BCRh
03h
1. X = Don’t care; RA = Read Address, RD = Read Data, ID = Device Code, SRD = Status Register Data, PA
= Program Address; PD = Program Data, QA = Query Address, QD = Query Data, BA = Any address in the
Block, BCR = Burst Configuration Register value.
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