M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Command interface
4.4
Read Status Register command
The Read Status Register command is used to read the status register. One bus write cycle
is required to issue the Read Status Register command. Once the command is issued
subsequent bus read operations read the status register until another command is issued.
The status register information is present on the output data bus (DQ1-DQ7) when Chip
Enable E and Output Enable G are at VIL and Output Disable is at VIH.
An interactive update of the status register bits is possible by toggling Output Enable or
Output Disable. It is also possible during a program or erase operation, by deactivating the
device with Chip Enable at VIH and then reactivating it with Chip Enable and Output Enable
at VIL and Output Disable at VIH.
The content of the status register may also be read at the completion of a program, erase or
suspend operation. During a Block Erase or Program command, DQ7 indicates the
program/erase controller status. It is valid until the operation is completed or suspended.
See the section on the status register and Table 11 for details on the definitions of the status
register bits.
4.5
Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the status
register to ‘0’. One bus write is required to issue the Clear Status Register command. Once
the command is issued the memory returns to its previous mode, subsequent bus read
operations continue to output the same data.
The bits in the status register are sticky and do not automatically return to ‘0’ when a new
Program or Erase command is issued. If any error occurs then it is essential to clear any
error bits in the status register by issuing the Clear Status Register command before
attempting a new Program, Erase or Resume command.
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