256Mb: 3V Embedded Parallel NOR Flash
Program/Erase Characteristics
Program/Erase Characteristics
Table 32: Program/Erase Characteristics
Notes 1 and 2 apply to the entire table
Parameter
Min
Typ
145
125
Max
400
Unit
Notes
3, 4
4
Chip erase
Chip erase
–
–
s
s
VPP/WP# =
VPPH
400
Block erase (128KB)
–
–
0.5
25
–
2
45
–
s
4, 5
Erase suspend latency time
Block erase timeout
µs
µs
µs
µs
50
–
Byte program
Single-byte program
16
50
200
200
4
4
Write to buffer program
(64 bytes at-a-time)
VPP/WP# =
VPPH
–
VPP/WP# =
VIH
–
70
200
µs
4
Word program
Single-word program
–
–
16
50
200
200
µs
µs
4
4
Write to buffer program
(32 bytes at-a-time)
VPP/WP# =
VPPH
VPP/WP# =
VIH
–
70
200
µs
4
Chip program (byte by byte)
–
540
270
25
13
15
10
5
800
400
200
50
60
40
15
–
s
4
4
Chip program (word by word)
Chip program (write to buffer program)
–
s
–
s
4, 6
4, 6
6
Chip program (write to buffer program with VPP/WP# = VPPH
)
–
s
s
Chip program (enhanced buffered program)
–
Chip program (enhanced buffered program with VPP/WP# = VPP)
Program suspend latency time
–
–
s
6
µs
PROGRAM/ERASE cycles (per block)
Data retention
100,000
20
–
cycles
years
–
–
1. Typical values measured at room temperature and nominal voltages and for not cycled
devices.
Notes:
2. Typical and maximum values are sampled, but not 100% tested.
3. Time needed to program the whole array at 0 is included.
4. Maximum value measured at worst case conditions for both temperature and VCC after
100,000 PROGRAM/ERASE cycles.
5. Block erase polling cycle time (see Data polling AC waveforms figure).
6. Intrinsic program timing, that means without the time required to execute the bus cy-
cles to load the PROGRAM commands.
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. B 5/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
85
© 2013 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
