256Mb: 3V Embedded Parallel NOR Flash
Registers
2. Block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set
to 0, the block is protected.
3. Block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0,
the block is protected.
Figure 22: Lock Register Program Flowchart
Start
ENTER LOCK REGISTER COMMAND SET
Address-data (unlock) cycle 1
Address-data (unlock) cycle 2
Address-data cycle 3
PROGRAM LOCK REGISTER
Address-data cycle 1
Address-data cycle 2
Polling algorithm
Yes
Done?
No
No
DQ5 = 1
Yes
Success:
Failure:
EXIT PROTECTION COMMAND SET
(Returns to device read mode)
Address-data cycle 1
READ/RESET
(Returns device to read mode)
Address-data cycle 2
1. Each lock register bit can be programmed only once.
Notes:
2. See the Block Protection Command Definitions table for address-data cycle details.
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. B 5/13 EN
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