128Mb 3V Embedded Parallel NOR Flash
Signal Assignments
Figure 3: 64-Ball Fortified BGA and 64-Ball TBGA
1
A
RFU
B
RFU
C
RFU
D
RFU
E
RFU
F
V
CCQ
G
RFU
H
RFU
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
A3
A7 RY/BY# WE#
A9
A13
RFU
RFU
A13
A9
WE# RY/BY# A7
A3
RFU
B
A4
A17 V
PP
/WP# RST#
A6
A18
A21
A8
A12
A22
A22
A12
A8
RST# V
PP
/WP# A17
A21
A18
A6
A4
RFU
C
A2
A10
A14
RFU
RFU
A14
A10
A2
RFU
D
A1
A5
A20
A19
A11
A15
V
CCQ
V
SS
V
CCQ
V
SS
A15
A11
A19
A20
A5
A1
RFU
E
A0
D0
D2
D5
D7
A16
A16
D7
D5
D2
D0
A0
RFU
F
CE#
D8
D10
D12
D14 BYTE# RFU
RFU BYTE# D14
D12
D10
D8
CE#
V
CCQ
G
RFU
H
OE#
D9
D11
V
CC
D4
D13 D15/A-1 RFU
RFU D15/A-1 D13
V
CC
D4
D11
D9
OE#
V
SS
D1
D3
D6
V
SS
RFU
RFU
V
SS
D6
D3
D1
V
SS
RFU
Top view – ball side down
Bottom view – ball side up
Notes:
1. A[22] = A[MAX].
2. A-1 is the least significant address bit in x8 mode.
PDF: 09005aef84daa141
m29w_128mb.pdf - Rev. A 7/13 EN
9
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