128Mb 3V Embedded Parallel NOR Flash
General Description
General Description
The M29W is an asynchronous, uniform block, parallel NOR Flash memory device man-
ufactured on 90nm single-level cell (SLC) technology. READ, ERASE, and PROGRAM op-
erations are performed using a single low-voltage supply. Upon power-up, the device
defaults to read array mode.
The main memory array is divided into uniform blocks that can be erased independent-
ly so that valid data can be preserved while old data is purged. PROGRAM and ERASE
commands are written to the command interface of the memory. An on-chip program/
erase controller simplifies the process of programming or erasing the memory by taking
care of all special operations required to update the memory contents. The end of a
PROGRAM or ERASE operation can be detected and any error condition can be identi-
fied. The command set required to control the device is consistent with JEDEC stand-
ards.
CE#, OE#, and WE# control the bus operation of the device and enable a simple con-
nection to most microprocessors, often without additional logic.
The M29W supports asynchronous random read and page read from all blocks of the
array. It features a write to buffer program capability that improves throughput by pro-
gramming a buffer of 32 words in one command sequence. Also, in x16 mode, the en-
hanced buffered program capability improves throughput by programming 256 words
in one command sequence. The device V
PP
/WP# signal enables faster programming.
The device contains a 128-word (x16) and 256-byte (x8) extended memory block. The
user can program this additional space and then protect it to permanently secure the
contents. The device also features different levels of hardware and software protection
to secure blocks from unwanted modification.
Figure 1: 128 Logic Diagram
V
CC
V
CCQ
V
PP
/WP#
15
A[22:0]
WE#
CE#
OE#
RST#
BYTE#
V
SS
DQ[14:0]
DQ15/A-1
RY/BY#
PDF: 09005aef84daa141
m29w_128mb.pdf - Rev. A 7/13 EN
7
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