128Mb 3V Embedded Parallel NOR Flash
Program/Erase Characteristics
Program/Erase Characteristics
Table 32: Program/Erase Characteristics
Notes 1 and 2 apply to the entire table
Parameter
Min
Typ
40
0.5
25
–
Max
400
2
Unit
Notes
Chip erase
–
s
s
3
4
Block erase (128KB)
Erase suspend latency time
Block erase timeout
–
–
45
µs
µs
µs
µs
µs
µs
µs
µs
s
50
–
Byte program
Single-byte program
–
16
51
78
16
51
78
270
135
20
13
8
200
200
200
200
200
200
800
400
200
50
3
3
Write to buffer program VPP/WP# = VPPH
(64 bytes at a time)
–
VPP/WP# = VIH
–
3
Word program
Single-word program
–
3
Write to buffer program VPP/WP# = VPPH
(32 words at a time)
–
3
VPP/WP# = VIH
–
3
Chip program (byte by byte)
–
3
Chip program (word by word)
–
s
3
Chip program (write to buffer program)
Chip program (write to buffer program with VPP/WP# = VPPH
Chip program (enhanced buffered program)
–
s
3, 5
3, 5
5
)
–
s
–
40
s
Chip program (enhanced buffered program with VPP/WP# = VPPH
)
–
–
5
25
s
5
Program suspend latency time
5
15
µs
cycles
years
PROGRAM/ERASE cycles (per block)
Data retention
100,000
20
–
–
–
–
1. Typical values measured at room temperature and nominal voltages and for not cycled
devices.
Notes:
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after
100,000 PROGRAM/ERASE cycles.
4. Block erase polling cycle time (see Data polling AC waveforms figure).
5. Intrinsic program timing, that means without the time required to execute the bus cy-
cles to load the PROGRAM commands.
PDF: 09005aef84daa141
m29w_128mb.pdf - Rev. A 7/13 EN
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