128Mb 3V Embedded Parallel NOR Flash
Common Flash Interface
Table 18: Device Geometry Definition (Continued)
Address
x16
x8
Data
Description
Value
31h
32h
33h
34h
62h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase block region 2 information
Erase block region 3 information
Erase block region 4 information
0
0
0
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Table 19: Primary Algorithm-Specific Extended Query Table
Note 1 applies to the entire table
Address
x16
40h
41h
42h
43h
44h
45h
x8
Data
0050h
0052h
0049h
0031h
0033h
000Dh
Description
Value
"P"
"R"
"I"
80h
82h
84h
86h
88h
8Ah
Primary algorithm extended query table unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
"1"
"3"
Address sensitive unlock (bits[1:0]):
00 = Required
Yes
90nm
01 = Not required
Silicon revision number (bits[7:2])
46h
8Ch
0002h
Erase suspend:
2
00 = Not supported
01 = Read only
02 = Read and write
47h
48h
8Eh
90h
0001h
0000h
Block protection:
00 = Not supported
x = Number of blocks per group
1
Temporary block unprotect:
00 = Not supported
01 = Supported
00
49h
4Ah
92h
94h
0008h
0000h
Block protect/unprotect:
06 = M29W128GH/M29W128GL
06
–
Simultaneous operations:
Not supported
PDF: 09005aef84daa141
m29w_128mb.pdf - Rev. A 7/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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