256Mb: 3V Embedded Parallel NOR Flash
Protection Operations
Three Bus Write cycles are required to issue the Extended Memory Block command.
Once the command has been issued the device enters the extended memory block
mode where all bus read or program operations are conducted on the extended memo-
ry block. Once the device is in the extended block mode, the extended memory block is
addressed by using the addresses occupied by block 0 in the other operating modes (see
the Memory Map table).
The device remains in extended memory block mode until the EXIT EXTENDED MEM-
ORY BLOCK command is issued or power is removed from the device. After power-up or
hardware reset, the device reverts to read mode where the commands issued to the
block 0 address space will properly address block 0.
The extended memory block cannot be erased, and can be treated as one-time pro-
grammable (OTP) memory.
In extended block mode, Erase, Chip Erase, Erase Suspend and Erase Resume com-
mands are not allowed.
To exit from the extended memory block mode the EXIT EXTENDED MEMORY BLOCK
command must be issued. This command requires four bus write cycles.
The extended memory block can be protected by setting the extended memory block
protection bit to 0 (see Lock Register); however once protected the protection cannot be
undone.
Note: When the device is in the extended memory block mode, the VPP/WP pin cannot
be used for fast programming and the unlock bypass mode is not available (see VPP//
WP).
EXIT PROTECTION Command
The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock
register, password protection, nonvolatile protection, volatile protection, and nonvola-
tile protection bit lock bit command set modes and return the device to read mode.
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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