256Mb: 3V Embedded Parallel NOR Flash
Features
List of Figures
Figure 1: Logic diagram ................................................................................................................................... 8
Figure 2: 56-Pin TSOP (Top View) .................................................................................................................... 9
Figure 3: 64-Pin Fortified BGA and 64-Pin TBGA ............................................................................................. 10
Figure 4: Block Addresses .............................................................................................................................. 13
Figure 5: Data Polling Flowchart .................................................................................................................... 22
Figure 6: Toggle Bit Flowchart ........................................................................................................................ 23
Figure 7: Status Register Polling Flowchart ..................................................................................................... 24
Figure 8: Lock Register Program Flowchart ..................................................................................................... 26
Figure 9: WRITE TO BUFFER PROGRAM Flowchart ........................................................................................ 35
Figure 10: ENHANCED BUFFERED PROGRAM Flowchart ............................................................................... 40
Figure 11: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 49
Figure 12: Software Protection Scheme .......................................................................................................... 55
Figure 13: Power-Up Timing .......................................................................................................................... 61
Figure 14: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 62
Figure 15: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 62
Figure 16: AC Measurement Load Circuit ....................................................................................................... 64
Figure 17: AC Measurement I/O Waveform ..................................................................................................... 64
Figure 18: Random Read AC Timing ............................................................................................................... 66
Figure 19: Page Read AC Timing ..................................................................................................................... 67
Figure 20: WE#-Controlled Program AC Timing .............................................................................................. 69
Figure 21: CE#-Controlled Program AC Timing ............................................................................................... 71
Figure 22: Accelerated Program AC Timing ..................................................................................................... 72
Figure 23: Data Polling AC Timing .................................................................................................................. 73
Figure 24: Toggle/Alternative Toggle Bit Polling AC Timing .............................................................................. 73
Figure 25: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 75
Figure 26: 64-Pin TBGA – 10mm x 13mm ........................................................................................................ 76
Figure 27: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 77
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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