256Mb: 3V Embedded Parallel NOR Flash
Bus Operations
Bus Operations
Table 9: Bus Operations
Notes 1 through 3 apply to entire table
Data Inputs/
Address Inputs
A[MAX], A[0]
Cell address
Command address
X
Outputs
DQ[15:0]
Data output
Data input5
High-Z
Operation
READ
CE#
OE#
L
WE#
RST#
H
VPP/WP#
L
L
H
L
X
X4
X
WRITE
H
H
STANDBY
H
L
X
X
H
H
OUTPUT
DISABLE
H
H
X
X
High-Z
RESET
X
X
X
L
X
X
High-Z
1. Typical glitches of less than 5ns on CE#, WE#, and RST# are ignored by the device and do
not affect bus operations.
Notes:
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. Dual operations are possible with the device multiple bank architecture. While program-
ming or erasing in one bank, read operations are possible in any of the other banks.
Write operations are only allowed in one bank at a time.
4. To write the four outermost parameter blocks (first two and the last two) VPP/WP# must
be equal to VIH.
5. Data input is required when issuing a command sequence or when performing data
polling or block protection.
Read
Bus READ operations read from the memory cells, registers, or CFI space. To accelerate
the READ operation, the memory array can be read in page mode where data is inter-
nally read and stored in a page buffer. Page size is 8 words and is addressed by address
inputs A[2:0].
A valid bus READ operation involves setting the desired address on the address inputs,
taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value.
(See AC Characteristics for details about when the output becomes valid.)
Write
Bus WRITE operations write to the command interface. A valid bus WRITE operation
begins by setting the desired address on the address inputs. The address inputs are
latched by the command interface on the falling edge of CE# or WE#, whichever occurs
last. The data I/Os are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE oper-
ation. (See AC Characteristics for timing requirement details.)
Standby and Automatic Standby
Driving CE# HIGH in read mode causes the device to enter standby, and data I/Os to be
High-Z. To reduce the supply current to the standby supply current (ICC2), CE# must be
held within VCC ±0.3V. (See DC Characteristics.)
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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