256Mb: 3V Embedded Parallel NOR Flash
Program/Erase Characteristics
Program/Erase Characteristics
Table 39: Program/Erase Characteristics
Notes 1 and 2 apply to the entire table
Parameter
Min
Typ
145
125
1
Max
400
400
4
Unit
Notes
Chip erase
–
s
3
3
Chip erase
VPP/WP# = VPPH
–
s
Block erase (128 Kword)
Block erase (32 Kword)
Erase suspend latency time
Block erase timeout
–
s
3, 4
–
0.37
25
–
1.5
45
s
–
µs
50
–
µs
Word program
Single-word program
–
16
50
70
270
25
13
15
10
5
200
200
200
400
200
50
µs
3
3
Write to buffer program
(32 words at-a-time)
VPP/WP# = VPPH
VPP/WP# = VIH
–
µs
–
µs
3
Chip program (word by word)
–
s
3
Chip program (write to buffer program)
–
s
3, 6
3, 5
5
Chip program (write to buffer program with VPP/WP# = VPPH
Chip program (enhanced buffered program)
)
–
s
s
–
60
Chip program (enhanced buffered program with VPP/WP# = VPP)
Program suspend latency time
–
–
40
s
5
15
µs
PROGRAM/ERASE cycles (per block)
Data retention
100,000
20
–
–
cycles
years
–
–
1. Typical values measured at room temperature and nominal voltages and for not cycled
devices.
Notes:
2. Typical and maximum values are sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after
100,000 PROGRAM/ERASE cycles.
4. Block erase polling cycle time (see Data polling AC waveforms figure).
5. Intrinsic program timing, that means without the time required to execute the bus cy-
cles to load the PROGRAM commands.
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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